Related Art 1
FIG. 18 is a sectional drawing of a conventional contact type image sensor (called CIS hereinafter) shown in a brochure published by "MITSUBISHI image sensor" (Mitsubishi Denki Kabushiki Kaisha, June 1987).
The conventional CIS of FIG. 18 comprises a light emitting diode array 1 (called LED array), a glass cover 2, an original document 3 placed on or passed over the glass cover 2, a rod lens array 4, a sensor board 5, a signal-processing circuit board 6 and a housing 7. The housing 7 encloses the LED array 1, the glass 2, the rod lens array 4, the sensor board 5 and the signal-processing circuit board 6 therein.
FIG. 19 is a block diagram of the conventional CIS.
In FIG. 19, a plurality of photoelectric conversion devices 9a to 9n and a signal circuit 5A are placed on the sensor board 5.
The signal circuit 5A is composed of shift registers and analog switches, and receives a parallel signal from the plurality of photoelectric conversion devices 9a to 9n. The plurality of photoelectric conversion devices 9a to 9n output the parallel signal depending on the shade of the original document. The signal circuit 5A converts the parallel signal to a serial signal.
The timing diagram in FIG. 20 explains operation of CIS shown in FIG. 19.
In FIG. 18, a light is generated from the light source of LED array 1, and the light is projected to the original document contacting the glass cover 2.
The reflected light depends on the shade of the original document. If an image of the original document is dark or black, the light is absorbed by it, so the reflected light does not go to the rod lens array 4.
In case that the image of the original document is light or white, the reflected light is strong, and is gathered in the rod lens array 4, and goes into the photoelectric conversion devices 9a to 9n in the sensor board 5 as an erect real image with one-to-one ratio.
Then a photoelectric current flows. The output goes to a terminal SIG of the signal-processing circuit board 6.
The voltage of the output signal is about 2 V when the original document is white. The voltage of the output signal is about 50 mV when the original document is black. Therefore, the s/n (signal/noise) ratio is about 30 dB.
In FIG. 19, n number of photoelectric conversion devices 9a to 9n are arranged side by side. Electric charges are generated at each of the photoelectric conversion devices 9a to 9n. The accumulated electric charges are converted to photoelectric currents at each of the photoelectric conversion devices 9a to 9n. An output voltage can be detected based on the level of the photoelectric current. Referring to FIGS. 19 and 20 the following is a description of how to detect the output voltage. A start pulse is input from the terminal SI, and a clock pulse is input from a terminal CLK. At the transitional timing point of the start pulse, the electric charges of each of the photoelectric conversion devices 9a to 9n flow sequentially as a photoelectric current in the signal line 6a. This photoelectric current is accumulated on the capacitor 6b of the signal-processing circuit board 6, and the output voltage is generated. This output voltage is amplified with the amplifier 6c about 10 to 20 times. The amplified voltage is output to the terminal SIG. This output voltage of the terminal SIG synchronizes with the clock pulse.
Thus, the image on the original document can be recognized by the output voltages.
FIG. 21 is a connection diagram of the sensor board 5 with sensor chips. Sensor chips 90a to 90n include the photoelectric conversion devices 9a to 9n. Each sensor chips 90a to 90n has a terminal CLK for a clock pulse and a terminal SI for a start pulse, and a terminal V.sub.DD for power supply and a terminal A.sub.GND for analog ground and a terminal SIG for signal output. The sensor board 5 is a printed-wiring board having a CLK line, a SI line, a V.sub.DD line (a power line), an analog ground line l.sub.2, and a signal line l.sub.1 on one side of the board. The terminals of the sensor chips 90a to 90n are connected with these corresponding lines as showing in FIG. 21.
FIG. 22 is a circuit diagram of the sensor chip 90a.
The sensor chip 90a has photoelectric conversion devices 9a to 9n, analog switches 11a to 11n, analog switches 10a to 10n, analog switch 12, flip-flops 13a to 13n, and AND gates G1 to Gn.
In FIG. 22, each of the photoelectric conversion devices 9a to 9n includes a transistor for current amplification and an electric charge accumulation part shown as a capacitor. The electric charge accumulation part accumulates the electric charges which are converted from light.
The analog switches 11a to 11n switch the signal of the photoelectric conversion devices 9a to 9n into the signal line L.sub.1 connected to the terminal SIG. The analog switches 10a to 10n discharge the unnecessary electric charges of the photoelectric conversion devices 9a to 9n. The analog switch 12 changes to "ON" at the positive-going edge of the clock pulse. The flip-flops 13a to 13n control each of the analog switches 10a to 10n and 11a to 11n with the clock pulse.
The operation of the circuit in FIG. 22 will be described below referring to the timing diagram in FIG. 23.
The start pulse from the terminal SI is input to the flip-flop 13a. This start pulse is synchronized with the clock pulse. The clock pulse is supplied to all flip-flops 13a to 13n from terminal CLK (CLOCK). The start pulse is shifted from the flip-flop 13a to the flip-flops 13b, 13c, . . . , 13n. In each timing point of shifting the start pulse from the flip-flop 13a to 13n, the electric charges of each of the photoelectric conversion devices 9a to 9n flow in the signal line L.sub.1 as photoelectric current. The voltage of this current corresponds to the amount of the electric charges.
As showing in FIG. 23, when the start pulse is entered to the D input in the flip-flop 13a, the Q1 output goes from "L" (LOW signal) to "H" (HIGH signal). The analog switch 11a changes to "ON" because the AND gate G1 goes "H". Then the electric charges of the photoelectric conversion device 9a flow to the signal line L.sub.1.
The next clock pulse is input to the AND gate G1. The analog switch 11a returns to "OFF" because the AND gate G1 changes to "L" at the positive-going edge of the next clock pulse. At this point, the signal line L.sub.1 is reset.
The Q2 output goes from "L" to "H" at the timing of the negative-going edge of the Q1 output. The analog switch 10a changes to "ON" by the complementary Q2 (not Q2) output. Therefore, the remaining electric charges in the photoelectric conversion device 9a are discharged to an analog ground line L.sub.2.
At the same time the analog switch 11b changes to "ON" because the Q2 output is "H". Then the electric charges in the photoelectric conversion device 9b flow in the signal line L.sub.1. Such operation continues as the start pulse is transmitted to the flip-flops in order.
The conventional contact type image sensor is composed as described above. In CIS, it is important that the output voltage which is generated by scanning a black image on the original document is low. The output voltage which is generated by scanning a black image is similar in magnitude to the output voltage generated by the dark current. Therefore, the output voltage is measured with respect to the voltage generated by the dark current. Hereinafter, "idling voltage" means the output voltage which is generated by dark current.
FIG. 24 shows an idling voltage measured using one sensor chip 90a. FIG. 25 shows an idling voltage measured using a conventional CIS which contains a plurality of sensor chips 90a to 90n.
The idling voltage Vd is measured at the output of the terminal SIG. The idling voltage measured in this case is based on the waveform of an oscilloscope. In FIGS. 24 and 25, the horizontal axis indicates the position of the photoelectric conversion devices. The vertical axis indicates the idling voltage.
As shown in FIG. 24 the idling voltage is not equal between adjacent photoelectric conversion devices.
As shown in FIG. 25, the idling voltage has a large fluctuation in the case where the photoelectric conversion devices are arranged in a long line on the sensor board 5.
As describe above, here are thus two problems.
(1) The idling voltage is not equal between adjacent photoelectric conversion devices.
(2) In case of arranging the photoelectric conversion devices in a long line, the idling voltage has a large fluctuation.
The reason is that unnecessary electric charges are accumulated in the signal line L.sub.1.
Related Art 2.
A contact type image sensor which eliminates above problems is shown in unexamined Japanese patent application HEI1-183257.
FIG. 26 is a circuit diagram of a sensor chip 100a. In FIG. 26, a plurality of analog switches 15a to 15n are added to the circuit shown in FIG. 22. These analog switches 15a to 15n control the timing point of discharge for the unnecessary electric charge which remains on the signal line L.sub.1. The signal line L.sub.1 is connected with terminal SIG. The analog ground line L.sub.2 is connected with terminal A.sub.GND. A plurality of lines are connected to the signal line L.sub.1 and the analog ground line L.sub.2. These lines correspond to the photoelectric conversion devices 9a to 9n. The analog switches 15a to 15n are arranged every line.
FIG. 27 illustrates a timing diagram of the output in the terminal SIG and the analog switches 15a to 15n. As shown in FIG. 27, each of the analog switches 15a to 15n changes its states between `ON` and `OFF` synchronous with the clock pulses. The analog switches 15a to 15n changes to "ON" at the positive-going edge of the clock pulse. Then the signal line L.sub.1 is connected to the analog ground line L.sub.2 by the analog switches 15a to 15n. As shown in FIG. 27, the output of the terminal SIG should go to "0" volt in theory when the analog switches 15a to 15n are "ON". Thus, the analog switches 15a to 15n discharge the unnecessary electric charge which remains on the signal line L.sub.1.
The following is the reason why a plurality of analog switches 15a to 15n are arranged corresponding to the photoelectric conversion devices 9a to 9n, which connect the signal line L.sub.1 and the analog ground line L.sub.2. The electric charges, generating from the photoelectric conversion devices 9a to 9n, flow in the signal line L.sub.1 as a photoelectric current. The relations between the voltage V.sub.P which generates in the signal line L.sub.1 and the photoelectric current i.sub.p are expressed by the following formula: EQU V.sub.P =K(h.sub.fe .times.i.sub.p .times.t.sub.s)/(C.sub.S +C.sub.L)(1)
V.sub.P : voltage PA1 i.sub.p : photoelectric current PA1 h.sub.fe : current amplification factor of the photo-transistor PA1 t.sub.s : storage time PA1 C.sub.S : stray capacitance PA1 C.sub.L : capacitance PA1 K: constant PA1 a plurality of sensor chips for sensing an image and outputting a signal to form a part of a parallel signal, wherein each of the sensor chips has a plurality of photoelectric conversion devices, an internal signal line coupled to the plurality of photoelectric conversion devices, an internal ground line coupled to the plurality of photoelectric conversion devices and a plurality of switches for coupling the signal line and the ground line; PA1 a printed circuit board for mounting the plurality of sensor chips thereon and for forming a signal circuit wherein the signal circuit receives the parallel signal from the plurality of sensor chips, converts the parallel signal to a serial signal, and outputs the serial signal; PA1 wherein the printed circuit board has a substrate as a base, a first conductor layer placed on one side of the substrate, having an external ground line coupled to the internal signal line, a second conductor layer having an external signal line coupled to the internal signal line, and an insulator layer between the first and the second conductor layers for creating a capacitance between the external signal line and the external ground line. PA1 a substrate; PA1 a first conductor layer placed on one side of the substrate for providing a ground; PA1 a second conductor layer for providing a signal line; PA1 an insulator layer located between the first and the second conductor layers for creating a capacitance between the signal line and the ground; PA1 a surface insulator layer; and PA1 a circuit mounted on the surface insulator layer having a plurality of chips electrically coupled to the signal line and the ground. PA1 forming a first conductor layer; PA1 forming a ground on the first conductor layer by chemical etching; PA1 forming an internal insulator layer next to the first conductor layer; PA1 forming a second conductor layer next to the insulator layer; PA1 forming a signal line on the second conduct layer by chemical etching; PA1 forming a surface insulator layer next to the second conductor layer; PA1 mounting chips on the surface insulator layer; and PA1 electrically coupling the chips to the signal line and ground.
The stray capacitances C.sub.S are distributed at various places between the signal line L.sub.1 and the analog ground line L.sub.2, as shown in FIG. 28. So, even though only one analog switch is arranged between the signal line L.sub.1 and the analog ground line L.sub.2, the unnecessary electric charge caused by these stray capacitances C.sub.S can not be removed completely when the signal line L.sub.1 is reset. In order to remove the influence of these stray capacitances C.sub.S, a plurality of analog switches 15a to 15n are arranged in a plurality of lines between the signal line L.sub.1 and the analog ground line L.sub.2 as shown in FIG. 26.
FIG. 29 is a block diagram of the sensor board 5. There are a plurality of sensor chips 100a to 100n, and a plurality of analog switches 150a to 150n. The analog switches 150a to 150n are arranged on the sensor board 5. On the other hand, the analog switches 15a to 15n are arranged in each of the sensor chips 100a to 100n. A signal line l.sub.1 and an analog ground line l.sub.2 are arranged on the sensor board 5. As shown in FIG. 26, a capital letter `L` is used for indicating lines within a sensor chip, such as signal line L.sub.1 and analog ground line L.sub.2. On the other hand, a small letter `l` is used for indicating lines on a sensor board, i.e. outside of the sensor chip, such as signal line l.sub.1 and analog ground line l.sub.2. The signal line l.sub.1 is connected with each sensor chips 100a to 100n and terminal SIG of the sensor board 5. An analog ground line l.sub.2 is connected with terminal A.sub.GND of the sensor board 5. There are a plurality of analog switches 150a to 150n between the signal line l.sub.1 and the analog ground line l.sub.2. These analog switches 150a to 150n control the timing point of discharge for the unnecessary electric charge which remains on the signal line 1.sub.1.